FET Channel Having a Strained Lattice Structure Along Multiple Surfaces

ABSTRACT

A channel  16  of a FinFET  10  has a channel core  24  and a channel envelope  32 , each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and Si x Gel 1-x , wherein 78&lt;x&lt;92. The channel core  24  has a top surface  26  of width w c  and an upstanding surface  28, 30  of height h c , preferably oriented 90° to one another. The channel envelope  32  is in contact with the top  26  and upstanding surfaces  28, 30  so that the area of interface is increased as compared to contact only along the top surface  26 , improving electrical conductivity and gate  18  control over the channel  16 . The height h c  can be tailored to enable a smaller scale FET  10  within a stabilized SRAM. Various methods of making the channel  16  are disclosed, including a mask and etch method, a handle wafer/carrier wafer method, and a shallow trench method. Embodiments and methods for FinFETs with one to four gates are disclosed.

TECHNICAL FIELD

These teachings relate generally to field effect transistors (FET)disposed on a semiconductor wafer or chip, in particular, to a layeredstructure as a channel that connects a source and a drain of a FET,wherein one of the layers is characterized by a strained latticestructure.

BACKGROUND OF THE INVENTION

Semiconductors and integrated circuit chips have become ubiquitouswithin many products due to their continually decreasing cost and size.Miniaturization in general allows increased performance (more processingper clock cycle and less heat generated) at lower power levels and lowercost. Present technology is at or approaching atomic-level scaling ofcertain micro-devices such as logic gates, FETs, capacitors, etc.Circuit chips with hundreds of millions of such devices are notuncommon. Further size reductions appear to be approaching the physicallimit of trace lines and micro-devices that are embedded upon and withintheir semiconductor substrates. The present invention is directed tosuch micro-sized FET devices. A FET is a transistor consisting of asource, a gate, and a drain. The action of the FET depends on the flowof majority carriers along a channel between the source and drain thatruns past the gate. Current through the channel, which is between thesource and drain, is controlled by the transverse electric field underthe gate. More than one gate may be used to more effectively control thechannel. The length of the gate determines how fast the FET switches andhow fast the circuit can operate, and is generally about the same as thelength of the channel (i.e., the distance between the source and drain).State of the art gate lengths are today on the order of 50 nm, and aremoving toward 10 nm within the next decade. Such size reductions shouldenable upwards of a billion devices on a single chip. However, suchsmall scaling necessitates greater control over performance issues suchas short channel effects, punch-through, and MOS leakage current.

Recently, the size of FETs has been successfully reduced through the useof one or more fin-shaped channels, known as fins. FETs employing finsare known as FinFETs. Previously, complementary metal-oxidesemiconductor (CMOS) devices were substantially planar along the surfaceof the semiconductor substrate, the exception being the FET gate thatwas disposed over the top of the channel. Fins break from that paradigmby using a vertical structure in order to maximize surface area of thechannel that is exposed to the gate. The gate controls the channel morestrongly because it extends over three sides of the fin shaped channel,rather than only across the top of a more traditional planar channel. Anexample of a FinFET is shown in FIG. 1, which is a TEM micrograph of aprior art FET with six fins. Each pair of fins comprises an NFET and aPFET.

One method to enhance fin performance is to fabricate fins in layers ofdisparate materials. One such exemplary device assigned to the assigneeof this invention is described in U.S. Pat. No. 6,252,284 B1,“Planarized Silicon Fin Device”, which is directed to controllingshort-channel effects.

Often, one of the layers of a multi-layered planarized FET fin isstrained silicon. It has been previously discovered that biaxiallystretching the crystalline lattice structure of silicon can speed theflow of electrons through a transistor, thereby enhancing performanceand decreasing power consumption. There is a natural tendency of atomsin layers of disparate materials to align with one another by stretchingand/or compressing their mismatched lattice structures along a planarinterface of the mismatch. Varying the respective thickness and chemicalcomposition of the materials aids in controlling the extent of extensionand compression in either material. As an example, FIG. 2 a depicts asilicon lattice structure and a germanium lattice structure, not toscale, in their natural (unstretched) states. When silicon is disposed(or grown) on a thicker layer of germanium, as in the SiGe compound ofFIG. 2 b, the lattice of silicon stretches while the lattice ofgermanium remains substantially unchanged, resulting in strainedsilicon. This result is achieved as the comparatively greater thicknessof the germanium layer yields greater structural integrity and greaterresistance to lattice compression. The actual process of latticestretching may also, or alternatively, entail atoms of Si and Geintermixed within a lattice structure. This integrates both atoms withina single layer, wherein the larger Ge atoms force the integrated latticestructure to stretch, as compared to a natural (unstretched) siliconlattice structure. The opposite effect from that shown in FIG. 2 b canalso be realized, wherein a thinner layer of germanium exhibits latticecompression when bonded to a thicker layer of silicon. Strained siliconhas been shown to enhance electron/hole mobility by up to 70% in NFETs,and up to 30% in PFETs. Other materials such as silicon germanium carbonmay be used to form the crystalline heterojunction that enhancesconductivity. There are several methods used to form strained layers,including chemical vapor deposition (CVD) and molecular beam epitaxy(MBE).

Strained silicon disposed along a plane has been used in prior artFinFETs. However, current leakage continues to be a limiting factor infurther scaling of FETs toward the atomic limit. Current leakage becomesan ascendant concern as miniaturization progresses because shorterlength FET gates, which generally track the channel length, have lessability to control electric charge carriers (holes or electrons).

The unintentional flow of charge carriers when the transistor is off istermed “current leakage.” Current leakage is the primary source of powerconsumed by an idle transistor. Current leakage may be classified intotwo types: MOS off current, wherein an unintended current passes throughthe channel despite the gate attempting to shut off current completely;and gate tunneling leakage current, wherein unintended current follows aparasitic pathway flowing into the channel, diffusions, or silicon body.As FET channel lengths continue to decrease, it is expected that gatetunneling leakage current will become a predominant concern fordesigners. The fin structure enhances gate control over the channel, butgate control over current is not absolute, even in prior art FinFETs.Compounding the current leakage problem, miniaturization enablesever-lower power levels that require more absolute gate control. Currentleakage that escapes the gate's control is less distinguishable fromintentional current, particularly at low current levels.

What is needed is a FET that allows small scaling with enhancedperformance for both NFETs and PFETs. Preferably, the FET should improvegate control in a fin structure that exhibits enhanced carrier transportproperties.

SUMMARY OF THE PREFERRED EMBODIMENTS

The foregoing and other problems are overcome, and other advantages arerealized, in accordance with the presently preferred embodiments ofthese teachings. The present invention concerns a channel forelectrically connecting a source and a drain of a field effecttransistor (FET), commonly called a fin for a FinFET. The channelincludes a channel core and a channel envelope. The channel core iscoupled to a substrate such as a SIMOX wafer (a wafer with an upperregion separated by implanted oxygen) or bonded wafer. The channel coredefines a top surface that is spaced from the substrate, and opposedsidewall surfaces between the substrate and the top surface. The channelcore is formed from a first semiconductor material defining a firstlattice structure.

The channel envelope is in contact with the opposed sidewall surfacesand the top surface of the channel core. The channel envelope is formedfrom a second semiconductor material defining a second lattice structurethat differs from the first lattice structure. This difference inlattice structure provides enhanced electrical conductivity due tostretching or compressing of the lattice structure. Preferably, the twomaterials are silicon and a silicon-germanium compound.

In another aspect of the present invention, the channel core defines atop and an adjoining side surface. In a preferred embodiment, the topsurface is the horizontal top and the side surface is one of twoupstanding sidewalls of the channel core, although two upstandingsurfaces extending from the substrate and meeting at a peak, or twosidewalls joined by a third lateral surface may be used. The channelcore comprises a first semiconductor material and the channel envelopecomprises a second semiconductor material that differs from the first.At least one of the first or second semiconductor materials exhibitsenhanced electrical conductivity due to one of a stretched or compressedlattice structure. The channel envelope is in contact with both the topand side surfaces, providing a larger area of interface between thedisparate lattice materials, as compared to prior art channels thatprovide interface only along a top surface. The exemplary materialsnoted above are operable to provide the stretched or compressed latticestructure.

The present invention also includes methods of making a FET channel. Inone such method, a substrate is provided with an overlying layer of afirst semiconductor material. A first channel core is defined from theoverlying layer, such as by a mask and etch technique. The channel coredefines a top surface spaced from the substrate and opposed first andsecond sidewalls between the substrate and the top surface. The methodfurther includes disposing a layer of second semiconductor material tocontact at least two of the surfaces (that is, at least two of the topsurface, the first sidewall and the second sidewall). Electricalconductivity through the layer of second semiconductor material, whichis different from the first, is enhanced by its contact with the channelcore. The layer of second semiconductor material may be deposited viavacuum deposition, or may be grown on a carrier wafer and separatedtherefrom to contact the appropriate surfaces of the channel core.

Another method of forming the channel includes providing a first layerof a semiconductor material over a substrate. This method includesdefining a trench in the overlayer, and the overlayer is then dividedinto a first section and a second section by the trench. The trench maybe filled with a buffer material such as TEOS (also known astetraethoxysilane, tetraethylorthosilicate, tetraethelorthosilicate, andtetrethoxysilicide). A portion of the second section is then removed toleave a remaining layer of first semiconductor material that has athickness less than a depth of the trench. This exposes a portion of thetrench. The method then includes disposing a layer of a secondsemiconductor material over the remaining layer and adjacent to thetrench. Exemplary semiconductor materials are discussed above.Preferably, the remaining layer is less than about 15 nm. Where thesecond semiconductor material is Si_(x)Ge_(1-x), the relativeconcentration of germanium may be chosen to promote thermal stability ofthe channel. Preferably, the germanium content is between about 8% andabout 22%, and most preferably between about 10% and about 20%, and alow temperature chemical vapor deposition process is used to form thelayer of second semi-conductor material.

Further, disclosed herein is a channel for electrically connecting asource and a drain of a field effect transistor (FET) comprising: achannel core comprising a bottom surface coupled to a substrate anddefining a top surface spaced from the substrate and opposed sidewallsurfaces between the bottom surface and the top surface, wherein thechannel core is formed from a first semiconductor material defining afirst lattice structure; and a channel envelope in contact with at leastone of the top surface, the bottom surface and one of the sidewallsurfaces (or combinations thereof), wherein the channel envelopecomprises a second semiconductor material comprising a strained latticestructure that differs from the first lattice structure, the channelenvelope being electrically coupled to a gate electrode. Preferably, thechannel is formed of a relaxed Si—Ge lattice, and the envelope is formedof a strained Si lattice.

An exemplary circuit SRAM circuit using FinFET in accordance with theteachings herein is disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other aspects of these teachings are made more evidentin the following Detailed Description of the Preferred Embodiments, whenread in conjunction with the attached Drawing Figures, wherein:

FIG. 1 is a TEM micrograph of a prior art FET with six fins;

FIGS. 2 a and 2 b, collectively referred to as FIG. 2, are prior artdiagrams showing how the lattice structure of silicon is strained whendisposed adjacent to germanium (FIG. 2 b) as opposed to its naturalstate (FIG. 2 a);

FIG. 3 is a block diagram depicting a FinFET in which the presentinvention may be disposed;

FIG. 4 is a sectional view of FIG. 3 along section lines 4′-4′;

FIGS. 5 a-5 f, collectively referred to as FIG. 5, are enlarged crosssectional views depicting one method of making a channel according tothe present invention, using masking and etching to deposit a channelenvelope onto a channel core;

FIGS. 6 a-6 h, collectively referred to as FIG. 6, are enlarged crosssectional views depicting an alternative method of making at least onechannel using a carrier wafer and a handle wafer;

FIGS. 7 a-7 f, collectively referred to as FIG. 7, are enlarged crosssectional views depicting an alternative method of making a channel fora PFET using a shallow trench;

FIG. 8 a-f, collectively referred to as FIG. 8, are perspective views ofvarious embodiments of FinFET devices; and

FIG. 9 depicts a SRAM circuit and is useful when discussingquantization.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1 and 2 a-2 b are described above and serve as context forunderstanding the present invention. FIG. 3 depicts in block diagram aFET 10. As known in the art, a source 12 and drain 14 are connectedelectrically via a channel 16, which is crossed by a gate 18. One ormore channels 16 and gates 18 may be present in a single FET 10. As usedherein, the length of the channel 16 is the distance from the source 12to the drain 14 as depicted in FIG. 3.

A sectional view of the channel 16 at section line 4′-4′ is depicted atFIG. 4. The FET 10 is disposed on a substrate 20 such as silicon 21overlain with a layer of buried oxide 22. A channel core 24 is made froma first semiconductor material disposed over the substrate 20. Thesubstrate 20 is preferably silicon based, such as a SIMOX wafer, abonded wafer, or CZ silicon (silicon wafer from the Czochralski process)as known in the art. Preferably, the channel core 24 is formed atop theburied oxide layer 22 that forms part of the substrate 20. The channelcore 24 defines a bottom surface 27 (shown as attached to the substrate20), a top surface 26 spaced from the substrate 20 and opposed sidewalls28, 30 disposed between the substrate 20 and the top surface 26. Thefirst semiconductor material from which the channel core 24 is madedefines a first natural crystalline lattice structure. As used herein,unless specifically noted otherwise, a natural lattice structure for aparticular material (element or compound) refers to the latticestructure of the particular material in question in its natural state,that is, without having been stretched, compressed, or otherwisestrained by external manipulation such as was previously described forstrained silicon. A compound exhibiting a relaxed lattice structure,wherein the relaxation is due only to annealing or other processing thatpurposefully removes tensile or compressive forces that would otherwisebe present, is not considered herein to be the natural state latticestructure.

A channel envelope 32 is disposed to substantially cover that portion ofthe channel core 24 that is not in direct contact with the substrate 20when the channel 16 is viewed in cross section, at least at the portionof the channel 16 crossed by the gate 18. Preferably, the channelenvelope 32 is coupled to the top surface 26 and both opposed sidewalls28, 30 of the channel core 24. The channel envelope 32 is formed from asecond semiconductor material that defines a second natural crystallinelattice structure that differs from the first lattice structure. Thedifferent natural lattice structures of the first and secondsemiconductor materials cause either tensile or compressive stresses atleast at the boundary of the channel core 24 and the channel envelope32. This mismatch of natural lattices, herein termed a “heterojunction,”facilitates carrier transport where the gate dielectric contacts theheterojunction stack. However, carrier transport is not necessarilymaximized at the heterojunction; the main channel for carrier transportmay alternately form within one or the other disparate materials, asknown in the art, depending upon several factors. The channel core 24defines a core width w_(c) and a core height h_(c). Similarly, thechannel envelope 32 defines an envelope width W_(e) and an envelopeheight h_(e). Any, or all, of these dimensions may be selected tooptimize or otherwise control the combined surface area of the opposedsidewalls 28, 30 and the top surface 26. Where the channel core 24and/or envelope 32 are not rectangular shaped (as primarily illustratedherein), such as when the channel core 24 is triangular and the channelenvelope 32 is disposed over two sides of the channel core 24, the widthand height are deemed to be averages for the particular component.Threshold voltage of a FET 10 using the inventive channel 16 describedherein can be selected based on the particular materials of either orboth of the first and second semiconductor materials, the presence of adopant in one or the other, or the core 24 and envelope 32 dimensions.

Preferably for a PFET, the first semiconductor material that comprisesthe channel core 24 is silicon, and the second semiconductor materialthat comprises the channel envelope 32 is a compound comprising siliconand germanium, such as Si_(0.7)Ge_(0.3). For a NFET, the firstsemiconductor material that comprises the channel core 24 is preferablya compound comprising silicon and germanium that is processed to exhibita relaxed lattice structure, and the second semiconductor material thatcomprises the channel envelope 32 is preferably silicon.

The gate 18, which may be formed of poly or metal or other material asknown in the art, is disposed over the channel 16 so as to contact thechannel envelope 32 through a dielectric layer 33, also termed a gatedielectric, disposed about the channel envelope 32. The dielectric layer33 may include an oxide, oxynitride, or rare earth oxide (e.g., hafniumoxide). The channel envelope 32 is disposed so as to preventsubstantial, and preferably complete, contact between the gate 18 andthe channel core 24.

FIG. 5 illustrates a preferred method for making a FET 10 in accordancewith the teachings herein. FIGS. 5 a-f depict one embodiment, whereinboth a PFET channel 34 and a NFET channel 36 are disposed on a singlesubstrate 20.

In FIG. 5 a, a substrate 20 including a buried oxide layer (BOX) 22 isprovided and overlain with a layer of a first semiconductor material 38,such as silicon. The combination of substrate layer 20, BOX layer 22,and layer of first semiconductor material 38 may be provided by a SIMOXwafer, may be a bonded wafer, or may be provided by a Czochralskiprocess as known in the art. In FIG. 5 b, a first channel core 40 and asecond channel core 42 are defined from the layer of first semiconductormaterial 38 by masking and etching, or by other means known in the art.The length and/or width of the first channel core 40 may differ fromthat of the second channel core 42. FIG. 5 c depicts a mask 44 (twomasks shown) over the second channel core 42 and over all areas exceptthe immediate vicinity of the first channel core 40. Etching or otherknown processes may be used to remove the mask 44 from contact withopposed sidewall surfaces of the first channel core 40, or to preventthe mask 44 from ever contacting such sidewalls. The first channel core40 will become the PFET channel 34.

FIG. 5 d depicts deposition of a layer of second semiconductor material46 over the entire wafer. Preferably, the layer of second semiconductormaterial 46 is a compound of Si and Ge that is deposited via ultra-highvacuum chemical vapor deposition (UHVCVD), but other chemical depositionprocesses are also compatible. Most preferably, the layer 46 defines athickness in the range of 5-10 nm, and the thickness of the layer 46 isdetermined by the concentration of germanium and criterion related tolayer thermal stability for such germanium concentration. The entity ofFIG. 5 d is planarized in FIG. 5 e to remove that portion of the entirelayer of second semiconductor material 46 that overlies the mask 44. Theremainder of the mask 44 is removed in FIG. 5 f; leaving the PFETchannel 34 and the adjacent NFET channel 36. More recently developedmethods deposit SiGe selectively on silicon. Using such a technique, aSiGe layer 46 can be selectively deposited on an exposed silicon channelcore 40 and any residual removed via a chemical etch. Where the layer offirst semiconductor material 38 is silicon and the layer of secondsemiconductor material 46 is Si_(x)Ge_(1-z), the channel envelope 32formed by the Si_(x)Ge_(1-x) compound is under compressive stress due tothe smaller natural lattice structure of the underlying Si layer 38.

An alternative method is depicted in FIG. 6. In FIG. 6 a, a handle wafer48 includes a buried oxide layer 22 as previously described, and anoverlying layer of first semiconductor material 38, such as silicon.FIG. 6 b depicts use of masking and etching to define to define one ormore trenches 47 adjacent to a remaining portion 38 a of the layer offirst semiconductor material 38. Considering the entire expanse of thehandle wafer 48, the trenches 47 and/or the remaining portions 38 a ofthe layer of first semiconductor material 38 may or may not becontiguous. Parallel to, or at a separate time from, the processingdepicted in FIGS. 6 a-6 b, a separate carrier wafer 50 is overlain witha layer of second semiconductor material 46, such as strained or relaxedSiGe, in FIG. 6 c. The carrier wafer 50 with overlayer 46 is thensubjected to ion implantation at FIG. 6 c. As known in the art,implantation with ions 52 such as hydrogen or boron ions allows theoverlayer 46 to be annealed and separated from the carrier wafer 50 at atemperature generally less than about 600° C., while also providing highquality SiGe free from dislocations. Nearly complete (≧95%) strainrelaxation of the SiGe layer 46 can also be achieved. The above processis generally known in the art as a “smart-cut” technique, and is moreparticularly described by Lijuan Huang et al, ELECTRON AND HOLE MOBILITYENHANCEMENT IN STRAINED SOI BY WAFER BONDING , IEEE Transactions onElectron Devices., vol. 49, no. 9, Sep. 2002, pp 1566-1571, hereinincorporated by reference. At FIG. 6 d, masking and etching are used todefine one or more islands 49 from the second layer of semiconductormaterial 46. The shapes of the islands 49 on the carrier wafer 50 arecomplementary to the shapes of the trenches 47 on the handle wafer 48.Preferably, a thin oxide layer 51 is disposed over at least the islands49 to facilitate later bonding to the handle wafer 48. Once the islands49 are formed, further processing may be according to known finfetprocessing techniques, such as, for example, sidewall image transfer.

FIG. 6 e depicts the structure of FIG. 6 d brought together with thestructure of FIG. 6 b. In FIG. 6 e, wherein the carrier wafer 50 isinverted over the handle wafer 48. The islands 49 and trenches 47 areprecision aligned with one another, preferably accurate to within 0.25microns. The anneal process described above for the smart-cut techniqueis employed to remove the islands 49 from the carrier wafer 50. Theislands 49 then lie within the trenches 47, and are bonded to the handlewafer 48 by the thin oxide layer 51. The carrier wafer 50 is removed,preferably for later reuse as a handle wafer after a high temperatureanneal and polishing. In some embodiments, vertical etches through theoverlayer 46 and selective ion implantation bounded by those verticaletches is used to combine more than one layer (more than one type ofsemiconductor material) into an island 49. Such an island 49 may bedisposed to match a recessed trench 47 on the handle wafer 48 aspreviously described, or it may be deposited on an elevated surface ofsilicon or other semiconductor material on the handle wafer 48. Theseembodiments result in a heterojunction of more than two layers, asdescribed more fully below.

FIG. 6 f shows smoothing of the exposed surfaces of the islands 49 andof the remaining portions 38 a, where these surfaces are opposite thehandle wafer 48. Smoothing and polishing is used to achieve asubstantially uniform height.

FIG. 6 g depicts a step wherein both the island 49 and the remainder 38a are masked and etched, or otherwise processed, to define one or morePFET channel cores 53 and preferably also one or more NFET channel cores55. While it is preferable to fabricate the PFET and NFET channelssimultaneously as described herein, the present invention does not sorequire. As shown in FIG. 6 h, an epitaxial layer of a semiconductormaterial different from the first semiconductor material is grown ordisposed on the PFET channel cores 53 to form channel envelopes 32,creating a strained silicon or other hetero-layer.

The material of the channel envelope 32 may be strained or unstrained,depending upon the desired properties of the resultant channel 16.Maximum lattice discontinuity occurs along the lines defined by eitherof the opposed sidewall surfaces 28, 30 and the bottom surface 27/topsurface 26 of the channel core 24.

Preferably, the PFET channel 34 or NFET channel 36 are characterized bya width of about 100-150 Å and a height of about 500-600 Å. Thesedimensions may change with scaling. Preferably, the strained lattice isdisposed along both the sidewalls 28, 30 and the top 26 of the PFETchannel 34 or NFET channel 36.

One particular application in which the carrier pathway along thestrained sidewall can be exploited is in a FET 10 in a static randomaccess memory (SRAM). SRAM is a type of memory that does not need to berefreshed like dynamic RAM (DRAM), so SRAM is generally much faster(typically about 10 ns for SRAM versus about 60 ns for DRAM) and morereliable. In addition, the cycle time (a measurement of how quickly twoback-to-back accesses of a memory chip can be made) of SRAM is muchshorter than that of DRAM because it does not need to pause betweenaccesses. The design of SRAMs generally assumes FETs in several fixedsizes (quantized). However, the width of the channel 16 is critical forstability in SRAM, and thereby imposes a trade off between size andstability. Rather than select a FET with a quantized channel width thatmay be larger in the x-y plane (the plane of FIG. 3) than desirable, aFET 10 employing a fin according to the present invention may be used tomodulate the height of the channel to enable a smaller FET 10 that stillensures SRAM stability. During fabrication, the starting silicon wouldbe at least as high as the highest estimated fin. Selective masking andetching of certain devices within a cell tailors fin height to achievethe desired SRAM stability. Preferably, a slow etch is used to ensureuniformity and fine control over fin height. Additionally, effectivechannel width can be adjusted by using multiple fins, preferably in aside-by-side relation.

FIG. 7 is a series of block diagrams showing process steps in forming aPFET. FIG. 7 depicts a shallow trench isolation (STI) that is imposedbetween a first semiconductor material, such as SiGe, and a secondsemiconductor material, such as Si. At FIG. 7 a, a substrate 20 supportsa buried oxide layer (BOX) 22, which is overlain with a layer of a firstsemiconductor material 38, such as silicon. The substrate/BOX/overlayercombination 70 may be a SIMOX wafer, a bonded wafer, or a CZ wafer aspreviously described and known in the art. At FIG. 7 b, a trench 58 isformed and filled with an oxide or other insulator such as TEOS, as isknown in the art. It is noted that the trenching and filling representedby FIG. 7 b is performed in several steps, and the trench 58 divides thelayer of first semiconductor material 38 into a first region 62 and aPFET region 64. Alternatively, the trench 58 may be etched, but notfilled, without departing from the advantages of the present invention.At FIG. 7 c, a mask layer 44 is selectively disposed over the trench 58and the first region 62 of the first semiconductor material. In FIG. 7d, the PFET region 64 is then etched back to a thin layer 60, preferablyto a thickness on the order of 10 nm. In FIG. 7 e, either before orafter the mask 44 is removed, a layer of second semiconductor material46 is disposed over the thin layer 60. As shown in FIG. 7 e, the thinlayer 60 includes a horizontal surface 67, and a substantially verticalsurface 68.

Preferably, the second semiconductor material 46 is SiGe of a moderateconcentration. For thermally stable fins, 10%-20% Ge concentration ispreferable when the thickness of the layer 46 is between about 10-30 nm.It has been found that thicker layers 46 of SiGe, and/or higherconcentrations of Ge, will be metastable and may require further thermalprocessing, though not annealing. Any embodiment of the presentinvention preferably includes an enveloping layer of gate dielectric orgate oxide. A channel 16 according to the present invention may be partof a FinFET 10, as in FIG. 3, and the FinFET 10 may preferably be partof an integrated circuit 100. The channel 16 may include a channel core24 that has substantially upstanding sidewalls 28, 30, a top surface 26,and a bottom surface 27, as in FIG. 4, or may be fabricated to defineonly a horizontal surface 67 and substantially vertical surfaces 68 asin FIG. 7 e. As a further alternative, shown in FIG. 7 f, the channel 16may have two sidewall surfaces 74 that extend from the substrate 22 andjoin at an acute or rounded peak 71 so as to define a substantiallytriangular cross section 75, as opposed to the rectangular crosssections illustrated herein, such as the cross section of the thin layer60. It is anticipated that a channel defining a non-orthogonal crosssection would be optimized using strained silicon on the top and incontact with the gate oxide. The channel envelope 32 may contact any twoof the surfaces 26, 27, 28, 30 of the channel core 24, or all suchsurfaces 26, 28, 30 not contacting the substrate 20. In any embodimentabove, a broader surface of the strained lattice structures that carrycharge (electrons or holes) is better exposed to the gate 18 as comparedto prior art FinFETs, enabling greater control by the gate 18 and moreefficient current transport.

FIG. 8 represents various additional embodiments of FinFET structures inaccordance with the teachings herein. In the embodiments shown in FIG.8, the structures include a relaxed Si—Ge layer with an overlyingstrained Si layer. This combination provides for improved electron-holemobility.

The channel 16 shown in FIGS. 8A-B, is formed of a channel core 24 andis overlain with the channel envelope 32, as is shown in FIG. 4. Asshown in FIG. 8, the substrate 20 includes the buried oxide layer 22,and the Si layer 21. Each structure depicted in FIG. 8 includes thesource 12, a drain 14, the gate 18, and the channel 16. Also shown is adielectric layer 33 disposed between the channel 16 and the variousgates. As the channel 16 is internal to the structures shown in FIGS.8C-E, and is therefore not visible, the channel 16 is only depicted inFIGS. 8A-B and 8F. Regardless, each of the embodiments of FIGS. 8A-8Fmay include the channel core 24 and channel envelope 32 as previouslydescribed.

In FIG. 8A, a single gate FinFET 90 is shown. In this embodiment, thechannel 16 includes a relaxed Si—Ge layer, and a strained Si layer. Athin oxide layer 33 is disposed between the channel 16 and a single gate95. FIG. 8B represents a double gate 91 embodiment of a FinFET. Inaddition to the single gate 95 shown in FIG. 8A, a second gate 96 ispresented. In this embodiment, the second gate 96, is buried within atrench in the buried oxide layer 22. FIG. 8C represents a triple gateFinFET 92, wherein a triple gate 97 is formed over the thin oxide layer33, which is disposed over the channel 16 (shown in FIGS. 8A-B). FIG. 8Drepresents a quadruple gate FinFET 93, wherein a quadruple gate 98effectively surrounds the channel 16. In FIG. 8D, a portion of thequadruple gate 98 is submerged in the buried oxide layer 22. In FIG. 8E,a FinFET 94 having a Pi gate 99 is shown. The Pi gate 99 extendsdownward, and at least partially into the buried oxide layer 22.

FIG. 8F is another embodiment of a double gate FinFET 87, defining afirst gate 88 and a second gate 89. The FinFET of FIG. 8F may be formed,for example, by polishing the FinFET of FIG. 8C until the portion of thetriple gate 97 of FIG. 8C that overlies the channel 16 is removed,leaving the two gates 88, 89 of FIG. 8F. Preferably, the channelincludes strained silicon germanium. One advantage in the gatearrangement of FIG. 8F is that each gate 88, 89 may be independentlycontrolled so that, for example, the first gate 88 is a typical FinFETgate and the second gate 89 may apply variable voltage. In this manner,the second gate 89 is a back gate to control a depletion region, whencurrent between the source 12 and drain 14 is switched between on andoff. Such a second gate 89 better controls leakages and performance ofthe first gate 88 by use of the variable voltage; so that only theminimum voltage necessary to control leakage current is applied.

Depositing the strained Si layer on the quadruple gate FinFET 93 and thePi gate FinFET 94, wherein the FinFET 93, 94 are PFET (and not NFET),improves mobility within the PFET, while preserving beneficial aspectsof the PFET and the NFET. Further it is noted that depositing strainedSi layers in the PFET in the [110] direction also improves the mobility.The [110] direction is at a 45° angle to the crystalline axes.

FIG. 9 depicts one embodiment of a six transistor SRAM unit cell. ForSRAM FinFET quantization, preferably, PFET quantization is carried outon the smallest device in a six-transistor conventional SRAM (e.g., NFETpass gate 77 (Pg) and pull-up PFET 76 (PL) is smaller in size). Thus,fin height quantization can be based on individual devices, or bucketingpass gate NFET and pull up PFET into one quanta height and larger NFET78 (Cc) into another. Alternatively, a smaller fin height, which isemployed in multiples of NFET and PFET devices of the embodiment shownin FIGS. 8A-F, may be used. This quantization will help to make a robustand stable cell.

While described in the context of presently preferred embodiments,various modifications of and alterations to the foregoing embodimentscan be made with normal skill in the art, and all such modifications andalterations remain within the scope of this invention and the ensuingclaims. Examples herein are considered to be illustrative and notexhaustive of the teachings of this invention.

1-18. (canceled)
 19. A Field Effect Transistor disposed on a substratecomprising: a source; a drain; a fin connecting the source to the drainand defining a channel core and a channel envelope; a gate coupledthrough a gate dielectric to at least two surfaces of the fin, whereinthe channel core defines at least two surfaces extending from thesubstrate and comprises a first semiconductor material, and the channelenvelope is in contact with the at least two surfaces and comprises asecond semiconductor material, and wherein at least one of the first orsecond semiconductor material exhibits one of a stretched and acompressed lattice structure.
 20. An integrated circuit comprising atleast one field effect transistor according to claim
 19. 21. A fieldeffect transistor (FET) comprising: a source, a drain, a channel, a gateelectrode, and a gate dielectric, wherein the channel comprises achannel core defining a bottom surface and a top surface spaced from thebottom surface by laterally opposed sidewall surfaces disposed betweenthe bottom surface and the top surface, wherein the channel corecomprises a first semiconductor material defining a first latticestructure; the channel further comprising a channel envelope in contactwith at least the top surface of the channel core, wherein the channelenvelope comprises a second semiconductor material defining a secondlattice structure that differs from the first lattice structure, whereinone of the first and second lattice structures is one of stretched andcompressed; and, wherein the gate electrode is coupled through the gatedielectric to the channel envelope only at a top surface of the channelenvelope that is opposed to the top surface of the channel core.
 22. TheFET of claim 21, wherein the first lattice structure is relaxed relativeto the second lattice structure.
 23. A field effect transistor (FET)comprising: a source, a drain, a channel, a gate electrode, and a gatedielectric; wherein the channel comprises a channel core defining abottom surface and a top surface spaced from the bottom surface bylaterally opposed sidewall surfaces disposed between the bottom surfaceand the top surface, wherein the channel core comprises a firstsemiconductor material defining a first lattice structure; the channelfurther comprising a channel envelope in contact with at least the topsurface of the channel core, wherein the channel envelope comprises asecond semiconductor material defining a second lattice structure thatdiffers from the first lattice structure; and, wherein the gateelectrode is coupled through the gate dielectric to the channel envelopeonly at surfaces of the channel envelope that are opposed to the top andbottom surfaces of the channel core.
 24. The FET of claim 23, whereinthe first lattice structure is relaxed relative to the second latticestructure.
 25. A field effect transistor (FET) comprising: a source, adrain, a channel, a gate electrode, and a gate dielectric; wherein thechannel comprises a channel core defining a bottom surface and a topsurface spaced from the bottom surface by laterally opposed sidewallsurfaces disposed between the bottom surface and the top surface,wherein the channel core comprises a first semiconductor materialdefining a first lattice structure; the channel further comprising achannel envelope in contact with at least the top surface and thesidewall surfaces, wherein the channel envelope comprises a secondsemiconductor material defining a second lattice structure that differsfrom the first lattice structure; and, wherein the gate electrode iscoupled through the gate dielectric to the channel envelope only atsurfaces of the channel envelope that are opposed to the top andsidewall surfaces of the channel core.
 26. The FET of claim 25, whereinthe first lattice structure is relaxed relative to the second latticestructure.
 27. A field effect transistor (FET) attached to a substratecomprising: a source, a drain, a channel, a gate electrode, and a gatedielectric; wherein the channel comprises a channel core defining abottom surface and a top surface spaced from the bottom surface bylaterally opposed sidewall surfaces disposed between the bottom surfaceand the top surface, wherein the channel core comprises a firstsemiconductor material defining a first lattice structure; the channelfurther comprising a channel envelope in contact with at least the topsurface, wherein the channel envelope comprises a second semiconductormaterial defining a second lattice structure that differs from the firstlattice structure; and, wherein the gate electrode is coupled throughthe gate dielectric to the channel envelope at surfaces opposed to thetop surface, sidewall surfaces and bottom surface of the channel core.28. The FET of claim 27, wherein the first lattice structure is relaxedrelative to the second lattice structure.
 29. A field effect transistor(FET) attached to a substrate comprising: a source, a drain, a channel,a gate electrode, and a gate dielectric; wherein the channel comprises achannel core defining a bottom surface and a top surface spaced from thebottom surface by laterally opposed sidewall surfaces disposed betweenthe bottom surface and the top surface, wherein the channel corecomprises a first semiconductor material defining a first latticestructure; the channel further comprising a channel envelope in contactwith at least the top surface, wherein the channel envelope comprises asecond semiconductor material defining a second lattice structure thatdiffers from the first lattice structure; and, wherein the gateelectrode is coupled through the gate dielectric to the channel envelopeat surfaces of the channel envelope that are opposed to the top,sidewall, and bottom surfaces of the channel core.
 30. The FET of claim29, wherein the first lattice structure is relaxed relative to thesecond lattice structure. 31-35. (canceled)